1. Field of the Invention
The present invention relates to an output circuit for use in a semiconductor IC (integrated circuit) and, more particularly, to an output control circuit which is connected to the input of a CMOS (complementary metal oxide semiconductor) output buffer.
2. Description of the Related Art
Recently there has been a need in the field of MOS IC for an IC which has a transfer delay time as long as that of a Schottky TTL (transistor-transistor logic), and outputs a large current. To meet this need, it is generally necessary to increase the transconductances of output buffer MOS FETs (field-effect transistors) P1 and N1 of such an output circuit as is illustrated in FIG. 1. When the transconductance of either MOS FET is increased, however, the DC resistance component of the MOS FET decreases. As a result of this, the output waveform of the output circuit is greatly influenced by the parasitic capacitance of the power-supply line or the output line of the output circuit, or by the inductive load of the output circuit. The deformation of the output waveform, either an overshoot or an undershoot, become too prominent. In order to reduce this deformation, an inductance element, such as ultra-high speed switching, planar diodes 102 and 103 or a ferrite bead 104, is connected to output signal line 101 of CMOS IC 100, as is illustrated in FIG. 2. In the case of such an output circuit having two or more output buffers BUFl to BUFn as is shown in FIG. 3, to reduce the deformation of the output waveform, resistance components R of gate lines 105 are utilized, thereby turning on buffers BUFl to BUFn sequentially, and moderating the change of the output waveform.
In the case of the output circuit shown in FIG. 2, planar diodes 102 and 103 or ferrite bead 104 is formed on the substrate, along with an IC. Also, in the case of the output circuit shown in FIG. 3, resistance components R are formed on the substrate, together with an IC. In either case, the substrate must be made larger. Since an IC device corresponding to, shown in FIG. 2 or FIG. 3 either requires additional elements for reducing the deformation of the output waveform, or a large substrate, it cannot be manufactured at sufficiently low cost.
Moreover, in the output circuit shown in FIG. 3, wherein the resistance components of the gate line serve to reduce the deformation of the output waveform, both the P-channel MOS transistor and the N-channel MOS transistor of each buffer, which are connected in series, are turned on when the output of the buffer changes (either from a low level to a high level, or vice versa). The two MOS transistors, which correspond to MOS FETs-P1 and N1 both shown in FIG. 1, remain on for a long period of time. During this period, a through current flows between the V.sub.DD power terminal and the ground terminal, via the N-channel MOS transistor and the P-channel MOS transistor. Hence, the power-supply potential and the ground potential (both within the IC) change, further deforming the output waveform of the output circuit.